1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device, and more particularly to a method for a selective formation of silicide films in a MOS field effect transistor.
2. Description of the Related Art
In the prior arts, it has been known to form silicide gate, source and drain electrodes by use of self-alignment technique on a MOS field effect transistor. A conventional fabrication method for a MOS field effect transistor with silicide gate, silicide source and silicide drain will hereinafter be described with reference to FIGS. 1A to 1C.
With reference to FIG. 1A, a field oxide film 102 is formed on a passive region of a p-type silicon substrate 101, while a gate oxide film 103 is formed on an active region of the p-type silicon substrate 101. A phosphorus-doped polysilicon film 104 is selectively formed on predetermined regions of the gate oxide film 103. An n-type impurity is implanted into an upper region of the silicon substrate 101 by a self-alignment technique with use of the phosphorus-doped polysilicon film as a mask to thereby form n.sup.- -type diffusion regions 105 in the upper region of the silicon substrate 101. A silicon oxide film having a thickness of 2000 angstroms is grown by a chemical vapor deposition on an entire surface of the device to subsequently be etched by anisotropic etching to form side wall oxide films having a thickness of 2000 angstroms at opposite sides of the individual polysilicon films 104. An ion-implantation of arsenic into the upper region of the p-type silicon substrate 101 is carried out by a self-alignment technique with use of the polysilicon films 104 and the side wall oxide films 106 as masks to thereby form n.sup.+ -type diffusion regions 107 serving as source and drain regions.
With reference to FIG. 1B, a spontaneous oxide film is removed by a buffered fluorine acid before a titanium layer 201 having a thickness of 1000 angstroms is formed by sputtering on an entire surface of the device.
With reference to FIG. 1C, the sputtered titanium layer 201 is subjected to a heat treatment in a nitrogen atmosphere so that the titanium layer 201 is partially reacted to the polysilicon film 104 and to the n.sup.+ -type diffusion regions 107 to thereby form titanium silicide layers 109 and 202 in an upper region of each of the polysilicon films 104 and in an upper region of each of the n.sup.+ -type diffusion regions 107. In this heat treatment, the titanium layer 201 is also reacted to the side wall oxide films 106 thereby thin titanium silicide films 401 are formed on the side wall oxide films 106. The thin titanium silicide films 401 are formed to be contact with the titanium silicide films 109 and 202 on the n.sup.+ -type diffusion regions 107. The unreacted titanium layer 201 remaining on the field oxide film 102 is removed by a wet etching.
Subsequently, an inter-layer insulator not illustrated is formed on an entire surface of the device and then contact holes are formed in the inter-layer insulator before aluminium electrodes.
The above described fabrication method is disclosed in the Japanese laid-open patent application No. 57-99775.
According to the conventional method as described above, the titanium layer 201 is forced to be reacted by the heat treatment to the side wall oxide films 106 thereby thin titanium silicide films 401 are formed on the side wall oxide films 106. The thin titanium silicide films 401 are formed to be electrically in contact with the titanium silicide films 109 and 202 on the n.sup.+ -type diffusion regions 107. The thin titanium silicide films 401 on the side wall oxide films 106 electrically connected to the titanium silicide layers 109 and 202 is no longer capable of permitting the transistor to show the normal operation.
To solve the above problem, it is required to remove the thin titanium silicide films 401 formed on the side wall oxide films 106. Actually, when removing the thin titanium silicide films 401 on the side wall oxide films 106, it is difficult to remove the thin titanium silicide films 401 only, and therefore not only the thin titanium silicide films 401 on the side wall oxide films 106 but also the titanium silicide films 109 and 202 are removed. Namely, a thickness of the titanium silicide films 109 and 202 is reduced thereby a sheet resistance is increased. The resulting value of the sheet resistance is made valuable thereby resulting in a difficulty of the transistor in showing the necessary performances. As a result, a yield of the transistor is also reduced.
To settle the above problem, there is a way to form silicon nitride side wall films on which the titanium silicide film is hard to be formed. Notwithstanding, the silicon nitride film has a large density of the trap center for carriers. For example, hot electrons generated at an end of the drain region are readily trapped into the silicon nitride film having the large trap center density. The trapped electrons in the silicon nitride side wall film may cause an increase of a sheet resistance of the lightly doped n.sup.- -type diffusion region 105 thereby resulting in a considerable deterioration of the performance of the MOS transistor. This may result in a lowering of the reliability of the MOS transistor.
By a scaling down of the device size, a distance between the polysilicon films 104 is also reduced thereby resulting in a deterioration of the step coverage of the titanium silicide film 202 formed by spattering between the polysilicon films 104 serving as gates. The deterioration of the step coverage of the titanium silicide film 202 may provide a reduction of a thickness of the titanium silicide film 202 formed by spattering. The reduction of the thickness of the titanium silicide film 202 may provide an increase of a sheet resistance of the titanium silicide film 202 and a deterioration of a heat resistivity thereof.